For circuits optimized for low-power, the power dissipated at the I/O (input/output circuit) is typically around 50% of the total power consumption. This I/O power dissipation is a consequence of relatively large dimensions of devices in the I/O pads and of the external-capacitances due to I/O pins, wires, and connected circuits. The devices in the I/O need to be large in order to drive the large external capacitances and this further increases their own parasitic capacitances. The capacitances on printed circuit boards are about two orders of magnitude larger than that inside of a chip. Dynamic charging and discharging these capacitances causes I/O pins to consume a relatively large amount of power.
Coding the I/O for lower power consumption has been utilized recently. Coding I/O for low power is practical and has been implemented in commercial chips. However, most of the conventional approaches are designed for parallel buses.